Intel completes Dept of Energy contract to develop memory technologies • The Register

The US Department of Energy’s Sandia National Labs believes a novel storage technology could hold the secret to faster and more accurate nuclear weapons simulations.

That’s why the authority awarded a research and development contract to Intel this week – a company that has systematically reduced its memory business in recent years.

The multi-year Advanced Memory Technology (AMT) program is funded by the DoE’s National Nuclear Security Administration (NNSA), tasked with maintaining the reliability and extending the life of the US strategic arsenal by enhancing its designs, its Mining and its destruction simulate potential with supercomputers.

And it’s not just nuclear weapons physics and materials analysis that NNSA is interested in. For example, the agency has developed models to simulate the turbulent airflow over a hypersonic missile delivering bad news to a city in the form of a warhead. Since these simulations often require myriad parameters to accurately predict the physics at play, Sandia believes they will likely benefit from improved memory performance.

With help from Los Alamos and Lawrence Livermore National Labs, the program will explore the deployment of “multiple technologies that have the potential to deliver more than 40 times the application performance of our future NNSA exascale systems,” said Thuc Hoang, director of Advanced Simulation and Computing, in a statement.

Why Intel?

The decision to work with Intel on the project is interesting, to say the least. The chipmaker is no stranger to novel memory architectures, as multiple generations of scalable Xeon processors now support tiered and persistent memory via the Optane line.

Funnily enough, Intel ended that line of business this summer, just a few years after its partner Micron stopped producing the 3D XPoint memory modules used in its products. Chipzilla also doesn’t have a NAND flash business. This division was sold to SK hynix in 2020.

To be fair to Intel, you don’t need a family of commercial products to do research and development in this area.

According to Intel colleague Josh Fryman, much of the program will be devoted to exploring ways to squeeze more performance out of standard DRAM memory.

“Our goal with the AMT program is to transform the organization of DRAM and help DRAM vendors design and deliver superior products,” he said The registry. “The growth in concurrency of computing devices is outpacing the growth in concurrency of DRAM fabrics. This should change for current and future platforms to deliver higher performance and be more power efficient.”

The DoE program is just beginning as the industry prepares for the leap from DDR4 to DDR5 DRAM, with the release of the first compatible data center processors from AMD this fall and Intel early next year. In addition to supporting much larger capacities – potentially up to 768GB per DIMM – DDR5 is also significantly faster than the previous generation.

The growth in parallelism of computing devices is outpacing the growth in parallelism of DRAM structures

With at least 4,800 megatransfers per second, this memory has been in the consumer market for more than a year and its bandwidth per DIMM is at least 50 percent higher than DDR4. Storage vendors, including Micron, expect to eventually boost this to up to 8,800 MTps.

Intel plans to bring findings from the research program back to the JEDEC industry consortium that oversees DRAM memory standards, Fryman said.

Beyond DRAM

Faster DRAM with lower latency isn’t the only technology that could make its way into the program. “We anticipate that technologies resulting from our AMT work will be orthogonal to CXL,” Fryman said.

Intel was instrumental in developing the Compute Express Link (CXL) interconnect, early applications of which include memory expansion, pooling, and tiered memory use cases.

For example, CXL memory expansion modules from Astera Labs, Samsung and others promise similar functionality to Intel’s now-defunct Optane persistent memory modules – albeit with much lower latencies and higher bandwidth.

Intel is also among the first to bake high-bandwidth memory (HBM) on a mainstream CPU. The company’s recently announced Xeon Max CPUs plug up to 64GB of HBM2e directly into the package, giving it around 1TB/s of memory bandwidth. The processors will be integrated into Argonne National Labs’ Aurora supercomputer.

However, this does not necessarily mean that any of these technologies will actually be used as part of the DoE program. ® Intel completes Dept of Energy contract to develop memory technologies • The Register

Rick Schindler

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