New TSMC 3DFabric Alliance aims to boost chiplet designs • The Register

AMD turned to advanced packaging to create chiplet designs and become a formidable CPU player again. Apple used the technology to boost the performance of its M1 Ultra chip. And Intel is betting its future success on 2D and 3D multi-die packaging technologies as part of its ambitious comeback plan.

Now, TSMC, the world’s largest contract chip manufacturer, aims to make chiplet-based products easier and faster to manufacture by leveraging its growing toolbox of advanced packaging technology, which has already benefited companies like AMD, Apple and others.

The Taiwanese foundry giant plans to achieve this through the formation of the 3DFabric Alliance announced on Thursday, which aims to help chip designers implement advanced packaging technology more quickly into their plans by working with partner companies that are critical to the development process meaning are.

The move is part of a new era in chip design, with companies migrating from monolithic chips to chiplet-based architectures to keep pace with increasing performance and efficiency demands for next-generation systems. For example, AMD’s Ryzen and Epyc chips have benefited from chiplet-based architectures for years, while Intel plans to turn to chiplets for future generations of processors.

TSMC’s partners cover several key elements of chip development, from electronic design automation and memory to substrates and testing. As part of the new alliance, they will gain early access to TSMC’s 3DFabric portfolio of 3D silicon stacking and advanced packaging technologies.

The goal is to enable these partners to develop new solutions in parallel with the development of TSMC’s 3DFabric technology so that chip designers can get their hands on the tools, technologies, materials and other resources required to create multi-die chip Make packages faster.

TSMC-Veep R&D LC Lu said while advanced packaging technologies “can open the door to a new era of chip-level and system-level innovation,” “extensive ecosystem collaboration” is needed to “help designers realize the… Best way through the countless options and approaches are available to them.”

“Through the collective leadership of TSMC and our ecosystem partners, our 3DFabric Alliance offers customers a simple and flexible way to unleash the power of 3D [integrated circuits] in their designs,” he added.

TSMC’s 3DFabric portfolio includes brand new technologies such as System-on-Integrated chips (SoIC) that underpin the 3D V-Cache technology in AMD’s Milan-X and Ryzen 7 5800X3D processors released this year.

The portfolio also includes older technologies: integrated fan-out and chip-on-wafer-on-substrate (CoWoS), which have received new iterations in recent years. Those using CoWoS include Nvidia and Amazon Web Services.

Representatives from AMD, Nvidia and AWS endorsed the new alliance, which is one of several formed by TSMC as part of its Open Innovation Platform initiative.

“We have already seen the benefits of working with TSMC and its products [Open Innovation Platform] Partner on the world’s first TSMC SoIC-based CPUs, and we look forward to working even more closely together to advance the development of a robust chiplet stacking ecosystem for future generations of high-performance, energy-efficient chips,” said AMD Executive Mark Fuselier.

TSMC is behind the new alliance as Intel hopes to entice chip designers to use its own advanced packaging technologies through the rival chipmaker’s Intel Foundry Services business. A month ago, Intel CEO Pat Gelsinger said he believes the company’s EMIB and Foveros 2D and 3D multi-die packaging technologies are key to extending the lifespan of Moore’s Law.

Meanwhile, Samsung, TSMC’s biggest foundry competitor, has launched a task force to develop new advanced packaging solutions to become competitive in this space.

While the parts are coming together so more chip designers can create chips with advanced packaging, there is still work to be done in other areas. This includes standardizing the interconnect technology required to move data between chiplets on multi-die packages.

Recently, TSMC and several other major chipmakers formed a consortium around Universal Chiplet Interconnect Express, a new standard being developed by Intel that aims to do for chiplets what PCI-Express did for peripherals used in computer Motherboards are plugged in. ® New TSMC 3DFabric Alliance aims to boost chiplet designs • The Register

Rick Schindler

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